Excel to HTML
WEDNESDAY 4 MARCH 2026
3D
Session Chair: Hari Tagat, Samsung
08:30 - 10:30
Grand Peninsula B
08:30ISS-278
FlatFace: Improve face recognition by sharpness-aware minimization, Tanapat Ratchatorn, Institute of Science Tokyo (Japan); Masayuki Tanaka, Institute of Science Tokyo (Japan) [view abstract]
Margin-based Face Recognition (FR) has achieved remarkable performance by learning discriminative feature representations that ensure high intra-class compactness and inter-class separability. While most state-of-the-art methods focus on developing margin-based loss functions, improving model generalization performance is equally critical, especially under open-set conditions where test identities are absent from training data. Recent developments in learning algorithms have highlighted the sharpness of the loss surface as a key factor in reducing the generalization gap. Building on this, Sharpness-Aware Minimization (SAM) introduced a weight perturbation step to enhance generalization performance, with Adaptive Adversarial Cross-Entropy (AACE) further refining SAM by modifying the perturbation step. Inspired by those researches, we propose FlatFace, a novel training framework for face recognition that adopts weight perturbation into the training process. FlatFace consists of two key steps: the perturbation step, which perturbs model parameters in both the feature extractor and class weights toward the worst-case scenario, and the weight updating step, which uses the loss gradient at the perturbed feature extractor and class weights to update the parameters. By guiding the model toward flatter minima, FlatFace improves generalization performance and accuracy, particularly for open-set face recognition tasks. Empirical experiments confirm its effectiveness, demonstrating reduced generalization gaps and enhanced overall performance.
08:50ISS-279
A structured light 3D imaging system integrated with polarization based deep networks for enhancing 3D reconstruction, Tzung-Han Lin, National Taiwan University of Science and Technology (Taiwan (Greater China)) [view abstract]
This paper investigates the integration of deep learning techniques with polarized imaging for robust 3D reconstruction, particularly targeting the challenges encountered in low-light environments and with highly reflective surfaces circumstances that often undermine the reliability of traditional 3D reconstruction methods. We present a structured-light 3D scanning system comprising a polarization camera and a projector, designed to streamline the acquisition of comprehensive datasets for AI model training. The prototype system is fabricated with an automated calibration scheme to establish the projection transformation between the polarization camera coordinate system and the 3D coordinate system of the target object. Additionally, sub-pixel localization algorithms are incorporated to enhance the spatial resolution of retrieved 3D point clouds, thereby ensuring the fidelity of ground-truth data for learning tasks involving 3D geometry.
09:10ISS-280
Tracking complex gestures with multimodal sensors, Yang Cai, Visual Intel Studio (US); Hsu-Wei Chen, UC San Diego (US) [view abstract]
This study examines a new multimodal motion capture interface that supports real-time operation and training without the need for wearable equipment. We measured gesture detection latency, key point requirements, and accuracy with LiDAR and webcam for complex gesture recognition. We focused on detection latency as an indicator of whether our gesture detection algorithm is suitable for operating in applications that require real-time responses.
09:30ISS-281
Application of linear-logarithmic response to a 4-tap iToF imager with storage diode structure for high light intensity tolerance, Gabriel Alcade, Shizuoka Univesity (Japan); Tomohiro Okuyama, Shizuoka University (Japan); Kamel Mars, Shizuoka Institute of Science and Technology (Japan); De Xing Lioe, Suicte (Japan); Keiichiro Kagawa, Shizuoka University (Japan); Keita Yasutomi, Shizuoka University (Japan); Shoji Kawahito, Shizuoka University (Japan) [view abstract]
Distance imaging sensors are essential for automotive cameras, human-machine interfaces, and consumer electronics, requiring extended measurement range, high resolution, and wide dynamic range under varying lighting and reflectance conditions. A critical challenge for short-range applications is sensor output saturation when measuring high-reflectance targets, leading to measurement failures that compromise system reliability.This work presents the first implementation of linear-log response characteristics in a 4-tap storage diode Time-of-Flight (ToF) sensor architecture to overcome saturation limitations. The key technical challenge addressed is developing a storage diode structure capable of implementing linear-log response to extend dynamic range while maintaining measurement accuracy across diverse illumination conditions.Unlike existing 4-tap ToF sensors with storage diodes that suffer from performance degradation under high illumination, this novel approach leverages logarithmic response characteristics to prevent saturation and ensure reliable distance measurement. The linear-log implementation represents a significant advancement in sensor capability, enabling accurate depth measurement across varying target reflectance and lighting environments. This advancement is essential for reliable operation in real-world applications where conventional sensors fail due to pixel saturation issues.
Event/SPAD/Time-Domain
Session Chair: Hari Tagat, Samsung
11:00 - 12:20
Grand Peninsula B
11:00ISS-282
An asynchronous time-based image sensor with a photovoltaic receptor, Pablo Fernandez-Peramo, University of Seville (Spain); Sergio Palomeque-Mangut, University of Seville (Spain); Angel Rodriguez-Vazquez, University of Seville (Spain); Juan Antonio Lenero-Bardallo, University of Seville (Spain) [view abstract]
Asynchronous Time-Based Image Sensors (ATIS) perform both temporal contrast detection and absolute exposure measurement within the region of interest, minimizing data throughput while providing just relevant data asynchronously with high temporal resolution. This work builds on this idea, and introduces a different front-end pixel design: The Photovoltaic Asynchronous Time-Based Image Sensor (PVATIS). PVATIS replaces the traditional front-end -- comprising two reverse-biased photodiodes and a logarithmic receptor -- with a single diode operating in the photovoltaic regime, combining both photodetection and logarithmic compression in a single self-biased device. This approach has the potential to address pixel-level crucial challenges by minimizing the pixel pitch, reducing noise, and lowering power consumption. All these benefits come at the expense of reducing the sensor's bandwidth due to a higher integrated capacitance. The complete paper will present insights into this architecture and results that demonstrate its operation.
11:20ISS-283
Circuit flicker noise modeling for pixels in event-based vision sensors, Daisuke Saito, OMNIVISION Technologies Inc. (US); Xiaozheng Mou, OMNIVISION Technologies Co., Ltd. (China (Mainland)); Menghan Guo, OMNIVISION Technologies Co., Ltd. (China (Mainland)); Dahai Zhou, OMNIVISION Technologies Co., Ltd. (China (Mainland)); Boyd Fowler, OMNIVISION Technologies Inc. (US) [view abstract]
Event-based vision sensors (EVS) are gaining interest in applications requiring low-latency, high-dynamic-range, and energy-efficient imaging, such as image deblurring, object detection for autonomous vehicles, and AR/VR glasses. Unlike conventional frame-based sensors, this performance is highly sensitive to device-level noise processes, especially in low-light scenes. In previous work, we proposed a framework of pixel-wise parameter estimation for EVS characterization. We introduced a physics-based model and shot noise model, validated on a typical pixel setup. However, that model didn t explicitly account for flicker noise, despite it being one of the major noise sources in modern CMOS technologies a key factor behind pixel-to-pixel variability and spurious noisy pixels, whose strength depends strongly on the technology. In this paper, we introduce a dedicated flicker-noise component in the previously developed EVS simulator. We calibrated the circuit flicker noise model using circuit-level simulations and sensor measurements, achieving an error margin of less than 20%. This model reproduced EVS circuit noise statistics and generated realistic synthetic event streams. The result indicated that flicker noise was larger than expected values from the SPICE simulation by a factor of three. Our work enables circuit-level trade-offs and offers intuitive noise visualizations for both hardware designers and algorithm developers to assess algorithmic impact.
11:40ISS-284
Time domain continuous imaging using LED sensels, Alyssa Oretel, University of Kentucky (US); Henry Dietz, University of Kentucky (US); Paul Eberhart, University of Kentucky (US) [view abstract]
Time domain continuous imaging (TDCI) centers on the capture and representation of time-varying image data not as a series of frames, but as a compressed continuous waveform per pixel. A high-dynamic-range (HDR) image can be computationally synthesized from TDCI data to represent any virtual exposure interval covered by the waveforms, thus allowing both exposure start time and shutter speed to be selected arbitrarily after capture, which also enables extraction of video with arbitrary framerate and shutter angle. Unfortunately, conventional sensors cannot directly implement TDCI capture, so earlier work focused on postprocessing conventional sensor output to approximate TDCI streams.The current work describes the first direct implementation of TDCI sensing. The sensors discussed here are not image sensor chips, but prototype equivalent circuitry and control logic as low pixel count board-level sensor modules constructed using commodity components. An LED is used to implement each sensel, and each is sampled asynchronously independent of all other sensels by reverse biasing the LED to charge its inherent capacitance and then timing how long the photocurrent takes to reach a fixed threshold voltage. These open source LED-based TDCI sensor modules are used to construct stand-alone TDCI cameras, allowing performance measurements, tweaking of the control logic, and empirically verifying that true TDCI sensing is practical.
12:00ISS-285
Asynchronous event-based sensors (EBS): A case study for infrared (IR) readout integrated circuits (ROIC) optimized for high sensitivity, event throughput and optimized system bandwidth/power consumption, Roman Fragasse, SenseICs Corporation (US); Megan Manifold, SenseICs Corporation (US); Ramy Tantawy, SenseICs Corporation (US); Shane Smith, SenseICs Corporation (US); Jonathan Bergey, JSB Solutions LLC (US) [view abstract]
Event-based Sensors (EBS) are imagers whose operation aims to mimic the human eye, wherein only changes within a scene are detected and subsequently processed. The resulting asynchronous intrascenic pixel changes that are detected with a high photon-to-digital gain and stamped with an X-Y coordinate and accurate timestamp enable drastic system bandwidth and power reduction. The SenseICs development for EBS applications has primarily been focused on the Infrared (IR) imaging space with silicon-validated IP developed for Readout ICs (ROICs) that can support a wide range of wavelengths from visible (VIS) to near-infrared (NIR), short-wave IR (SWIR), mid-wave IR (MWIR) and long-wave IR (LWIR). This paper will present several important sensor design tradeoffs including pixel unit cell architectures and system-level bandwidth and power optimization. The paper will then present conclusions based on silicon-validated results from the existing SenseICs IP.
Hybrid/Global Shutter Sensors
Session Chair: Hari Tagat, Samsung
15:30 - 16:30
Grand Peninsula B
15:30ISS-287
A 3-stacked hybrid-shutter CMOS image sensor with driver-integrated signal delivery enhancement for high-resolution global operation, Su-Hyun Han, Samsung Electronics, Semiconductor, R&D Center (Republic of Korea); Hyukbin Kwon, Samsung Electronics, Semiconductor, R&D Center; Sung-Jae Byun, Samsung Electronics, Semiconductor, R&D Center; Daehee Bae, Samsung Electronics, Semiconductor, R&D Center; Gihwan Cho, Samsung Electronics, Semiconductor, R&D Center; Sanggwon Lee, Samsung Electronics, Semiconductor, R&D Center; Yong-Suk Choi, Samsung Electronics, Semiconductor, R&D Center; Si-Gyoung Koo, Samsung Electronics, Semiconductor, R&D Center; Heesung Shim, Samsung Electronics, Semiconductor, R&D Center; Min-Woong Seo, Samsung Electronics, Semiconductor, R&D Center; Jae-kyu Lee, Samsung Electronics, Semiconductor, R&D Center; Jonghyun Go, Samsung Electronics, Semiconductor, R&D Center [view abstract]
This paper presents the world s first 3-stacked hybrid shutter (HS) CMOS image sensor (CIS) for mobile application, featuring switchable operations between 0.6 m 4-photodiode 1.2 m-pitch 50Mp rolling shutter (RS) and 2.4 m-pitch 12.5Mp global shutter (GS). In the GS mode, where all sensors drive the entire row simultaneously, this sensor has leveraged innovative multi-state (MS) technology to improve the settling time of global signals, despite the load capacitance being larger by a factor equal to the number of rows compared to RS mode. This paper includes an analysis of the challenges encountered during the operation of the charge pump and negative transfer gate(NTG) regulator in GS mode, along with a guide for designing regulator for GS mode. This sensor achieves 52ke- full well capacity (FWC) and 2.4e- random noise (RN) in GS mode. While GS is more susceptible to noise compared to RS mode, it has effectively addressed this issue through its advanced 3-stack structure and high-capacity DRAM capacitor.
15:50ISS-288
A 72-dB SNR 1K-fps global shutter CMOS image sensor with dual pixel reset voltage and programmable gain amplifier, Kota Ogino, Tohoku University (Japan); Takezo Mawaki, Tohoku University (Japan); Rufuto Koba, Tohoku University (Japan); Ken Miyauchi, Tohoku University (Japan); Yushi Sakai, Tohoku University (Japan); Rihito Kuroda, Tohoku University (Japan) [view abstract]
This study presents a high-speed global shutter CMOS image sensor (CIS) designed for absorptive imaging applications requiring detection of small light amount differences. The sensor integrates a dual pixel reset voltage mechanism and a column programmable gain amplifier, enabling high-resolution readout under strong illumination. Fabricated using a 0.18 um CMOS process, the CIS features a two-stage lateral overflow integration capacitor pixel architecture, trench-type sample-and-hold capacitors, and correlated multiple sampling for low-noise performance. Experimental results demonstrate a dynamic range of 128 dB and a maximum signal-to-noise ratio (SNR) of 72 dB at 1000 fps. Imaging examples confirm gain-dependent SNR enhancement and amplifier input range trade-offs. Comparative analysis shows the developed CIS achieves a superior figure of merit relative to previously reported global shutter CIS, highlighting its potential for high-precision spectroscopic and fluid concentration distribution measurements.
16:10ISS-289
A global shutter proximity capacitance CMOS image sensor for high-precision and high-speed capacitance Imaging, Hiroto Ogura, Tohoku University (Japan); Ukyo Kotake, Tohoku University (Japan); Takezo Mawaki, Tohoku University (Japan); Ken Miyauchi, Tohoku University (Japan); Rihito Kuroda, Tohoku University (Japan) [view abstract]
This work presents a newly developed global shutter proximity capacitance CMOS image sensor for simultaneously achieving high-precision and high-speed capacitance imaging performances. Capacitance sensors are utilized for applications such as the inspection of metal wiring for flat-panel-display and printed circuit board and the cell monitoring, where both high detection accuracy and high-speed inspection are required. Fabricated using a 0.18 um CMOS process, the developed chip achieves global shutter operation with 12 um^H x 6 um^V pixels by utilizing in-pixel voltage-domain memories comprised with high-density trench capacitors. A high detection precision of 170 zF detection lower limit and a high-speed operation at 90 fps were confirmed by its global shutter operation. This result signifies that the developed chip achieves a comparable level of precision at a speed more than three times faster than conventional rolling shutter-type proximity capacitance CMOS sensors. Furthermore, distortion-free capacitance imaging of moving objects was confirmed.
Panel Discussion: Can We Still Trust Our Eyes? Securing the Truth with Capture-Level Authentication
16:30 - 17:30
Grand Peninsula B
Panel Discussion: Can We Still Trust Our Eyes? Securing the Truth with Capture-Level Authentication, Joyce Farrell, Stanford University (US; Chiao Liu, Meta Reality Labs (US); Boyd Fowler; Hany Farid, UC Berkely (US)
In an era of ubiquitous deepfakes and generative AI, how do we prove a video is a "fact" and not a "fabrication"? Join us for a critical discussion on hardware-enforced provenance—the technology that signs and secures images at the very moment of capture. From citizen journalism to courtroom evidence, the stakes for visual integrity have never been higher. This panel explores the cutting edge of on-chip encryption and the path toward making "tamper-proof" the new industry standard. Moderator: Joyce Farrell (Stanford University); The Forensics Expert: Hany Farid (UC Berkeley), world-renowned pioneer in digital forensics and image analysis; The Sensor Architect: Boyd Fowler (Former CTO, OmniVision), leading authority on CMOS image sensor design and hardware security; The Systems Visionary: Chiao Liu (Director of Research, Meta Reality Labs), expert in the hardware-silicon roadmaps and system architectures for future AR/VR platforms. Panel discussion moderator: Joyce Farrell, Stanford University. Participants: Chiao Liu, Director of Research at Meta Reality Labs; Boyd Fowler, former CTO of OmniVision; Hany Farid, UC Berkeley Professor & GetReal Co-founder
THURSDAY 5 MARCH 2026
Fabrication and Analysis
Session Chair: Jon McElvain, Meta
08:30 - 10:30
Grand Peninsula B
08:30ISS-290
Numerical calculation of coupling capacitances in image sensor cells with CellCap3D, Valery Axelrad, SEQUOIA Design Systems, Inc. (US Territories and Minor Outlying Islands); Ognjen Milic, [view abstract]
Image sensors have become a cornerstone of modern imaging technology, with applications spanning from consumer electronics like smartphones and digital cameras to advanced scientific instrumentation, automotive systems, and healthcare. The performance of these sensors is determined by properties of the underlying image sensor cells, where capacitive coupling plays a critical role in signal detection and processing. In this paper, we present a comprehensive approach to numerically calculate coupling capacitances in image sensor cells using the novel simulation tool, CellCap3D. This method offers significant advantages in terms of accuracy, efficiency, and adaptability for the design and optimization of next-generation image sensor arrays. CellCap3D s ability to use periodic boundary conditions provides unparalleled efficiency of simulation of periodic image sensor arrays in comparison to conventional reflective boundary conditions when an array (typically 3x3) must be included in the analysis.
08:50ISS-291
Yield enhancement in production of CMOS image sensors: Defect analysis and solutions, Liviu Oniciuc, Forza Silicon (AMETEK Inc.) (US); Abhinav Agarwal, Forza Silicon (AMETEK Inc.) (US); Joseph Valenzuela, Forza Silicon (AMETEK Inc.) (US); Daniel Chica, Forza Silicon (AMETEK Inc.) (US); Loc Truong, Forza Silicon (AMETEK Inc.) (US) [view abstract]
This report outlines an aspect of the yield analysis and optimization efforts undertaken by Forza Silicon and foundry partners throughout the image sensor production process. Beginning with design and wafer fabrication, the process includes detailed characterization, wafer probing, and final testing, with all image and data results stored locally for analysis. Through a new method using full wafer image mosaic at probe recurring issue were identified. One such issue was defective pixel error density increasing toward the wafer edge. The root cause was traced to contact resistance linked to oxidation at the pixel output stages. Collaborative efforts with the wafer fabrication vendor led to process modifications, including a new cleaning step and recipe adjustments. Comparative analysis between reference and modified wafers showed significant yield improvements and elimination of border defect patterns. Other refinements for this project addressed center die failures and color channel inconsistencies, particularly in the blue filter coating. These findings have been incorporated into the production flow, enhancing overall sensor reliability and yield. Forza Silicon continues to provide integrated production services with a strong focus on yield optimization.
09:10ISS-292
Nano-light pillar structure applied on 1.6 um pixel size of CMOS image sensor for high sensitivity, Chun-Yuan Wang, VisEra Technologies Company (Taiwan (Greater China)); Chung-Hsuan Yu, VisEra Tecgnologies Company (Taiwan (Greater China)); Ken Chou, VisEra Technologies Company (Taiwan (Greater China)); Yu-Shen Lu, VisEra Technologies Company (Taiwan (Greater China)); Hao-Wei Liu, VisEra Technologies Company (Taiwan (Greater China)); Jian Wen Luo, VisEra Technologies Company (Taiwan (Greater China)); Shin-Hong Kuo, VisEra Technologies Company (Taiwan (Greater China)); Yuchi Chang, VisEra Technologies Company (Taiwan (Greater China)); Huang-Jen Chen, VisEra Technologies Company (Taiwan (Greater China)); Po-Hsiang Wang, VisEra Technologies Company (Taiwan (Greater China)); Peter Chiu, VisEra Technologies Company (Taiwan (Greater China)); JB. Lin, VisEra Technologies Company (Taiwan (Greater China)); Chin-Chuan Hsieh, VisEra Technologies Company (Taiwan (Greater China)) [view abstract]
We demonstrated a die-level CMOS image sensor featuring 1.6 mm pixels and integrated nano-light pillars. This design achieved a 1.5 dB improvement in the signal-to-noise ratio (SNR). With an optimal pillar arrangement, the efficiency ratio between the die center and ide edge is comparable to conventional image sensors, while maintaining an acceptable Gr-Gb signal difference.
09:30ISS-293
Full-Stokes imaging with integrated metasurface sensors, Pawel Latawiec, Metalenz, Inc. (US); Masoud Pahlevaninezhad, Metalenz, Inc. (US); Rasoul Taghavi, Metalenz, Inc. [view abstract]
Metasurface-router pixel architectures have been demonstrated for various sensing modalities, including visible and linear polarimetric imaging. Especially within polarimetry, this system design has the advantage of improved transmission and reduced back-reflection into the imaging system. Here, we apply the design concept to full-Stokes polarimetric imaging and integrate an assembled optical module with an imaging pipeline for real time full-Stokes scene reconstruction at near-infrared (940 nm) wavelengths. We look at two general design approaches towards per-pixel polarimetry: a six-pixel octahedral selection and a four-pixel tetrahedral selection of the target analyzing Stokes vectors, and contrast their performance.
Special Application and Systems
Session Chair: Gloria Putnam, Vision Research and Forza Silicon
11:00 - 13:00
Grand Peninsula B
11:00ISS-294
From photon detection to high-speed output: Performance and integration trade-offs in SPAD and CMOS image sensors., Steven Huang, SWIRL Corporatoin (US); Daniel Van Blerkom, SWIRL Corporation (US); Sam Bagwell, SWIRL Corporation (US); Jonathan Bergey, JSB Solutions LLC [view abstract]
This paper presents a comprehensive study that compares the optoelectronic performance of single-photon avalanche diodes (SPADs) and CMOS image sensors (CIS) in high-speed imaging applications, outlining operating regimes where each technology offers distinct advantages. Differences in readout architecture, including in-pixel processing, pixel-to-periphery transfer, and high-speed multiplexing, are analyzed to identify bandwidth and latency trade-offs. The study further examines output-driver limitations and signal-integrity challenges when interfacing these imagers with modern FPGA-based acquisition systems, where impedance control and timing margins constrain achievable data rates. Packaging considerations for managing thermal load and maintaining electrical performance at multi-Gbit/sec speeds are also discussed. Experimental results from recent test-chip prototypes validate the comparative models. Finally, future directions are proposed, focusing on high-dynamic-range SPAD arrays and CIS photodiodes optimized for reduced carrier-transfer time, enabling next-generation high-speed imaging sensors that balance sensitivity, power efficiency, and integration complexity.
11:20ISS-295
Accelerating camera design & vision system specification through end-to-end simulation, Julie Buquet, Immervision (Canada); Teodor Todorov, Immervision (Bulgaria); Xiaojun Du, Immervision (Canada); Simon Thibault, Immervision/ Universite Laval (Canada); Patrice Roulet, Immervision (Canada) [view abstract]
Designing vision systems for human vision and learning-based applications require early validation and optimization aligned with task-specific Key Performance Indicators (KPIs). Current simulation tools are typically limited to final-stage validation due to their reliance on complete designs and expert-level inputs.We present an end-to-end simulation pipeline that enables rapid evaluation of vision systems, bridging the gap between the application requirements and the system design. The pipeline integrates optical modeling, sensor simulation, Image Signal Processing emulation, and learning-based task performance assessment making informed decision-making accessible.We proved the reliability of the toolkit by comparing the simulation s image quality metrics MTF, SNR, color reproduction with those from a physical camera module. Across all metrics, deviations remained below module-to-module variation.Using a drone navigation example, we illustrate how we used the tool to guide the design process, from early distortion curve design, sensor selection, to color correction tuning; all before building any prototypes. By allowing to iterate and optimize vision systems virtually, we significantly reduced development time and cost and ensured optimum vision for the final product.In this talk, we will present how end-to-end simulation accelerates, derisks and streamlines: system design, Component Selection, hardware build iterations, manufacturing errors, Hardware/Software integration, IQ Tuning.
11:40ISS-296
Simulating autofluorescence imaging systems for oral health monitoring, Joyce Farrell; Brian Wandell, Stanford University (US) [view abstract]
Simulation enables virtual testing and optimization of imaging system components, facilitating efficient engineering design. This presentation describes the integration of computational models of oral mucosal tissue fluorescence with simulations of excitation sources, optical filters, and sensor quantum efficiency, producing virtual prototypes of autofluorescence imaging systems. By optimizing imaging configurations within these simulations, we can increase fluorescence signal quality and improve the detection of oral mucosal abnormalities. Predictive modeling of system performance prior to manufacturing reduces our dependency on physical prototypes, streamlines the development process, and accelerates the deployment of advanced imaging solutions for oral health monitoring.
12:00ISS-297
Optimizing object detection performance with complete image system simulations, [view abstract]
>Optical systems development requires software tools to design lenses, mechanics, sensors and image signal processing pipelines. Traditionally, these tools are operated independently from each other and do not provide insights into the complete system performance, thus causing time and cost inefficiencies as extra resources are spent designing, building and testing hardware prototypes that may either not meet, or drastically exceed, system requirements. For instance, optical systems are often over-designed in one or multiple facets such as the lens design tolerance, sensor bit-depth, or image signal processing complexity to ensure all requirements are met for the final application. By using end-to-end simulations, it is possible to eliminate these inefficiencies and accelerate the time-to-market for an optical system. In this work we simulate a complete imaging system and we demonstrate a method to simulate the minimally viable solution that meets the performance requirements of an object-detection application. > This is accomplished by using an imaging system simulator, ImSym, to model the complete system. Effects of the lens model, detector characteristics including noise, ISP routines, and stray light effects are combined to produce images to validate product performance prior to hardware builds.
12:20ISS-354
JIST-first-2025-010: Evaluation of SOI lock-in pixels with improved modulation contrast, Yudai Shinohara, Shizuoka University; Keita Yasutomi, Shizuoka University; Ryo Imai, Shizuoka University; Keiichiro Kagawa, Shizuoka University; Shoji Kawahito, Shizuoka University [view abstract]
Time-resolved imaging requires image sensors with high-speed modulation and a thick sensing layer for high sensitivity to near-infrared light and high-energy photon and particle detection. A solution is a silicon-on-insulator (SOI) based lock-in pixel with a fully depleted thick substrate; however, such pixels suffer from degraded modulation contrast due to high parasitic light sensitivity (PLS) in the floating diffusions. This work presents a pixel architecture that suppresses the PLS while preserving fast charge transfer by introducing a shallow buried channel and intermediate gates that enhance the lateral electric field. A prototype four-tap pixel array was fabricated using 0.2 m SOI technology and experimentally characterized under 940 nm pulsed laser illumination. The proposed structure achieved a modulation contrast of 92.5 % and PLS below 1.2 % under 40 ns gate-pulse operation, maintaining stable performance up to 35,000 electrons per pulse, demonstrating suitability for X-ray and electron-beam imaging.
Novel Architecture and Circuit Design
14:00 - 15:00
Session Chair: Abhinav Agarwal, Forza Silicon
Grand Peninsula B
14:00ISS-298
Embedded charge domain neural network for sensors to enable low-power edge computing, [view abstract]
Charge-domain AI-in-Sensor processing represents a breakthrough in neural-network hardware for imaging and edge applications. By integrating sensor elements directly into neural layers, AIStorm has eliminated analog-to-digital conversion and data movement, dramatically lowering latency, power, and cost. Charge-domain neurons manipulate electronic charge as the computational medium, achieving up to up to 600x higher TOPS/W vs. competing technologies. Dynamic weight reconfiguration and recursive reuse deliver always-on continuous inference capabilities. This approach redefines edge AI and mobile, offering robust, low-power, sensor-integrated intelligence for real-time applications across consumer, industrial, automotive, and environmental domains.
14:20ISS-299
Highly shrinkable PhotoGate pixel with optimum full well capacity and charges transfer, Louis Stephan, STMicroelectronics (France); Jean-Pierre Carrere, STMicroelectronics (France); Pierre Malinge, STMicroelectronics (France); Matteo Vignetti, STMicroelectronics (France); Edgar Perez, STMicroelectronics (France); Christine Augier, STMicroelectronics (France); Emilie De Pretto, STMicroelectronics (France); Eric Vire, STMicroelectronics (France); Guo Neng Lu, Universite Claude Bernard Lyon 1, Institut des Nanotechnologies de Lyon (France) [view abstract]
For developing high-resolution CMOS image sensors by reducing pixel sizes, the photogate architecture enables the construction of small pixels offering an excellent compromise between full well capacity (FWC) and transfer efficiency. This work demonstrates that the shape of the Vertical Transfer Gate (VEGA) significantly influences performance. Excellent results are achieved with a U-shaped VEGA, and guidelines are also provided to obtain good transfer efficiency with simple I-shaped VEGA architecture, suitable for the smallest pixels. A pixel with over 10 ke- FWC at 0.72 m pitch is demonstrated, featuring low dark current and minimal lag, which is promising for further reducing pixel pitch.
14:40ISS-300
A low noise CMOS image sensor with in-pixel OTA and intra-scene HDR feature, Pengfei Xu, KU Leuven (Belgium); Idham Hafizh, KU Leuven (Belgium); Guy Meynants, KU Leuven (Belgium) [view abstract]
A low noise CMOS image sensor (CIS) with intra-scene HDR feature is presented. The design employs in-pixel 5-transistor (5T) operational transconductance amplifier (OTA) in open-loop configuration to achieve high gain to amplify a weak signal under low illumination. A unity-gain configuration is adopted for high level illumination, and it can avoid saturation at the output, thereby enhancing the overall dynamic range. OTA offset cancellation is realized using an auto-zeroing MOS capacitor placed in the unused pixel area outside the photodiode and OTA. Noise suppression is further enhanced through analog correlated double sampling (CDS) in the column programmable gain amplifier (PGA) and digital CDS after analog-to-digital conversion, effectively reducing kTC noise, low-frequency noise, and offset. The proposed design offers a promising reference for future CIS architectures employing stacking technologies to integrate pixel-parallel ADCs, ultimately aiming to achieve low-noise, global shutter digital pixel sensors without the use of special device technology such as SPAD. A demonstrator was developed using 180nm CIS process, which has 96 256 OTA pixels and 512 column readout chains for characterization purposes.