Instructors: Bilal Zafar, Talha Tahir, and Sohaib Imran Bhatti, 10xEngineers
Level: Intermediate
Prerequisites: Bayer Image Sensors, image processing basics, rudimentary knowledge of digital camera pipelines; programming: C/C++ & Python.

Benefits:
This course enables the attendee to:

• Gain insights into how ISP blocks such as dead pixel correction, demosaicing, denoising, sharpening, and more work in a pipeline.
• Develop practical experience writing CUDA kernels, memory management (global, shared), and thread/block optimization for ISP blocks.
• Learn techniques to optimize memory, reduce kernel launch overhead, and pipeline multiple stages for real-time throughput.
• Make a hands-on comparison of CPU vs. GPU implementation in terms of speed, latency, and power efficiency.
• Build a foundation if you want to explore ISP + AI approaches for NVIDIA GPUs.

Course Description:
This course provides a practical introduction to porting image signal processing (ISP) pipelines to NVIDIA GPUs using CUDA. Participants learn how to design and optimize GPU kernels for core ISP algorithms, while gaining concepts like memory management, GPU threads/blocks, and performance profiling. Participants learn how to use parallelized and optimized ISP algorithms for achieving high throughput to enable an ISP to run on GPU-enabled hardware rather than porting the ISP for an FPGA for achieving real-time performance. The course enables participants to leverage ISP blocks before any AI/ML model to achieve better performance and detection accuracy by improving the quality of the image that is being input to the AI/ML model.

Intended Audience: AI researchers, Imaging and CV experts, GPU / CUDA developers:
AI researchers: Learn to accelerate and optimize image preprocessing on GPUs, enabling faster and higher-quality inputs for vision and multimodal AI models.
Imaging and CV experts: Develop the skills to port and optimize ISP algorithms for efficient execution on GPU architectures
GPU/CUDA developers: For developers already comfortable with CUDA but less familiar with imaging, this course provides a concrete and high-impact application domain.

Bilal Zafar is the co-founder and CEO of 10xEngineers, a hardware design services company specializing in RISC-V microprocessors and camera image-signal processors. Previously, Zafar was principal engineer at Qualcomm, where he co-led a world-wide team working on developing custom and semi-custom IPs. He holds an MS and PhD in computer engineering from the University of Southern California, Los Angeles, and a BSc in electronics engineering from the GIK Institute of Engineering Sciences & Technology.

Talha Tahir is an experienced engineer at 10xEngineers specializing in GPU programming and Image Signal Processing (ISP) acceleration. He has extensive expertise in writing ISP kernels in CUDA for NVIDIA GPUs and porting ISP algorithms to C++ and CUDA for high-performance imaging applications.

Sohaib Imran Bhatti is a Staff Engineer at 10xEngineers, where he has led the development of Infinite-ISP, an open-source hardware ISP development suite. He now is responsible for the development of CUDA-ISP, focusing on accelerating imaging pipelines on NVIDIA GPUs. He successfully delivered the Infinite-ISP course at EI 2025, showcasing its end-to-end imaging capabilities and now wants the world to know how to port ISPs on CUDA.